This invention relates generally to computer processor operation, and more particularly to providing a method, system, and computer program product for selectively accelerating early instruction processing.
Modern computer systems may include one or more processors that implement a processing technique known as pipeline processing (or pipelining) to further improve processing performance, such as speed and efficiency. Pipelining involves processing multiple commands (or instructions) concurrently in various processing stages instead of a more serial manner (e.g., one after the other). Although pipelining is beneficial, it is subject to errors (or hazards), for example, resulting from the concurrent processing of instructions or related data that are interdependent for proper processing results. One example of a pipelining hazard is a read-after-write (“RAW”) hazard, in which the result of processing a first instruction is needed to accurately process a second, concurrently processed instruction. In such hazards, if the second instruction is processed (e.g., the related data is read from memory) before the first instruction is sufficiently processed (e.g., before the resulting data is written to memory), the processing of the dependent second instruction may result in an error (e.g., if the processing is not sufficiently delayed), which degrades processor performance.
The decrease in processing speed resulting from RAW hazards can be worsened as the number of stages between the read stage(s) and the write stage(s) in the pipeline staging is increased (e.g., in faster pipelining designs), since the read processing for the dependent second instruction is thereby further delayed by the write processing for the first instruction. There are various approaches to minimize the consequences (or penalty) of RAW hazards, however, an increased amount of component space (or area), processing time (e.g., added delay or latency), and power consumption (collectively, “hardware overhead”) is needed for such approaches. Furthermore, some of these approaches implement an early instruction execution scheme that unpredictably causes additional RAW hazards while attempting to prevent such hazards. Thus, an approach to minimize the penalty of RAW hazards without the need for such hardware overhead or the potential to cause other such hazards is desirable.